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Simplify Multi-Core Debugging in Your SoC Development Workflow
Aaron Bauch (Field Application Engineer, IAR Systems)
Location: Room 204
Date: Thursday, August 29
Time: 3:15 pm - 4:00 pm
Track: ESC - Embedded Hardware Design & Verification
Format: Technical Session
Vault Recording: TBD
The complexity of applications is always increasing and to handle the increased workload, multicore devices are becoming more popular in SoC design. A modern debug solution can yield a surprisingly advanced visualization of your application's behavior using the Instrumentation Trace Macrocell (ITM) available in Cortex-M based microcontrollers. Additionally, utilizing the full Embedded Trace Macrocell (ETM) available in many Cortex-M/R/A devices adds even more possibilities to identify bugs in the most efficient way. In this session, we will look at the technology behind various ARM trace sources and use trace-based debugger technology to demonstrate the benefits of ARM Cortex-M/R/A debug features; specifically, we will show you how to do code coverage and function profiling on your device to quickly isolate issues. Additionally, this presentation will show you how to simultaneously debug two or more identical cores (symmetric multicore processing (SMP)), and two cores with different architectures (asymmetric multicore processing (AMP)), all in one single debug probe interface. This session will help you quickly and seamlessly deploy a SoC application.